In the search for high mobility materials to replace silicon (Si) in digital logic structures, much interest has gone to the development of germanium (Ge) channels, in particular strained Ge, due to the high carrier mobility characteristics of the material.
In order to ensure optimum mobility, essentially defect-free Ge is required, which further leads to the need for a defect-free surface onto which the Ge is produced. A typical technique for depositing a SiGe layer in a narrow trench is referred to as Aspect Ratio Trapping (ART). This typical technique allows filling of narrow trenches (e.g., trenches obtained by STI (Shallow Trench Isolation)) on a Si substrate, with a SiGe layer that does not show defects in the top part of the trenches. All defects observed originate on the Si/SiGe interface and become trapped by the STI sidewalls.
In “Fabrication of Low-Defectivity, Compressively strained Ge on Si0.2Ge0.8 Structures using Aspect Ratio Trapping,” Journal of the Electrochemical Society, 156(4)H249-H254 (2009), J.-S. Park et al. disclose using this technique, followed by the growth of strained Ge layers on the thus obtained SiGe structures. Optimization of the quality of the Ge-layer is done by performing a pre-baking step prior to Ge-growth.